Non-volatile semiconductor memory devices using semiconductor elements such as an EEPROM, an AND-type flash memory, a NOR-type flash memory, and a NAND-type flash memory are widely known. The NAND-type flash memory among them is advantageous in achieving high density as each memory cell shares a source/drain diffusion layer.
An end of a memory cell array of the NAND-type flash memory is provided with a select gate transistor for controlling selection and non-selection of a memory cell block. In order to achieve even higher density in the NAND-type flash memory, a space between gate electrodes of two adjacent select gate transistors may be reduced.
However, electrical contacts from upper layer electrode wiring to a substrate needs to be formed between the two adjacent select gate transistors. Thus, it is desirable to establish a manufacturing method in which a process margin in a process for forming the electrical contacts can be sufficiently secured even when the space between the gate electrodes of the select gate transistors is reduced.
As memory cells are scaled down, on the other hand, the capacitance between wirings, substrates, or between the wiring and the substrate within the memory cell array may cause a problem of degradation in device operation. In order to solve this problem, there is a method of forming air gaps in element isolation regions and between the gate electrodes.
Therefore, it is desired to establish the manufacturing method for realizing both: the formation of the air gaps in the element isolation regions and between the gate electrodes; and securing the process margin in the process for forming the electrical contacts.